The present invention relates to the areas of circuit design and simulation. In particular, the present invention provides a method and system for predicting a switching vector producing the worst-case inductive and capacitive noise.
Until recently, on-chip inductive signal noise hasn""t been considered in microprocessor designs. However, as device sizes continue to shrink, the role of inductive noise becomes more prominent, as the relative area of interconnect to device sizes becomes significant. New tools to analyze inductive noise are currently being developed in the semiconductor and CAD (xe2x80x9cComputer Aided Designxe2x80x9d) industry. Inductive signal noise is difficult to analyze due to the large number of signals that must be considered and the complex three-dimensional nature of the interconnect models that must be generated.
Inductive signal noise usually occurs in interconnects with low resistance, insufficient inductive shielding or over-driven lines. In addition, inductive noise can be of increased concern in wide busses where the signals can switch simultaneously. The inductive coupling can be especially problematic when all of these conditions are present.
As chip speeds continue to increase, neglecting inductive effects may put designs at risk. Just as capacitive coupling must be considered to calculate timing and noise, inductive coupling can be equally important. Mutual inductance impacts noise and timing just as mutual (cross) capacitance impacts noise and timing. In addition, inductive signal noise can potentially violate oxide integrity through repeated noise spikes.
If inductive signal noise is not taken into account, a design may fail. In particular, worst-case noise from capacitive and inductive noise combined can result in false switching. For digital circuits, in particular, it is desirable to determine a worst case switching vector with respect to a node of interest. A switching vector is a set of transition data for each of a set of signals that defines which direction (up or down) attacking signals will switch to obtain the highest magnitude noise pulse at one end (the node where inductive noise is of interest) of the victim line. Typically algorithms for predicting or computing worst-case switching vectors are implemented in software, i.e., running a computer simulation, retrieving data, analyzing the data and then computing the worst-case switching vector.
A key part of inductive noise analysis in on-chip signal grids is determining the true worst-case switching vector. Determining the correct worst-case vector is also important if design decisions (grid changes, driver resizing, etc) will be based on the trends seen in inductive noise. The true trend may be masked if the worst case switching vector changes when the structure itself is changed
To determine the worst-case switching vector given an interconnect model that includes inductance and capacitance requires some type of computer simulation. An intensive worst case analysis may be performed that considers all possible switching vectors, but this is too time consuming when considering the total number of possibilities multiplied by the simulation time for one case. In general, the search space to determine the worst case switching vector includes 2Nxe2x88x921 possibilities, where N is the number of signals under consideration. For instance, if there are 40 signals, then there are 239=approx. 550 billion combinations of falling/rising on the attackers. However, it may be possible to perform only Nxe2x88x921 simulations if the system under study involves regular structures. Simulation is computationally expensive especially for busses with many bits because the computation load of simulation versus the number of bits in the bus grows much faster than linearly. In any case, the brute force method for determining the worst-case switching vector should be replaced by an intelligent, knowledge driven process.
In particular, for on-chip interconnects, a large number of signals must be considered for inductive noise analysisxe2x80x94consequently determining the worst-case switching vector is of great importance in the design and development of signal grids. For instance, an on-chip signal bus may be 32, 64, or 128 bits wide and route together for long distances.
Another problem is in determining the worst case in a realistic route where bits in a bus (or a set of signals) can be interleaved along the length or swizzled at the boundary of a metal layer change. To determine the worst-case vector in this scenario would normally require utilizing a brute force trial and error process.
Because inductive noise is becoming more significant as device sizes shrink relative to interconnect, a new approach for accurately predicting worst case switching vector for inductive noise is necessary.